74LV74PW

edge triggered, D-type flip-flop, Si-gate, CMOS, TSSOP-14

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PartNumber:: 74LV74PW

Brand:: NXP Semiconductors - nxp | Pack: TSSOP | D/C: 06+

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Products Upload time: 2012-02-21

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Part Number:74LV74PW
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Product Summary

The 74LV74PW is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The 74LV74PW is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Parametrics

Absolute maximum ratings: (1)VCC, DC supply voltage: –0.5 to +7.0 V; (2)±IIK, DC input diode current at VI < –0.5 or VI > VCC + 0.5V: 20 mA; (3)±IOK, DC output diode current at VO < –0.5 or VO > VCC + 0.5V: 50 mA; (4)±IO, DC output source or sink current standard outputs at –0.5V < VO < VCC + 0.5V: 25 mA; (5)±IGND, ±ICC, DC VCC or GND current for types with standard outputs: 50 mA; (6)Tstg, Storage temperature range: –65 to +150 ℃ ; (7)Ptot, Power dissipation per package for temperature range: –40 to +125℃ : plastic DIL above +70℃ derate linearly with 12mW/K: 750 mW; plastic mini-pack (SO) above +70℃ derate linearly with 8 mW/K: 500mW; plastic shrink mini-pack (SSOP and TSSOP) above +60℃ derate linearly with 5.5 mW/K: 400mW.

Features

Features: (1)Wide operating voltage: 1.0 to 5.5V; (2)Optimized for Low Voltage applications: 1.0 to 3.6V; (3)Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V; (4)Typical VOLP (output ground bounce) < 0.8V @ VCC = 3.3V, Tamb = 25℃ ; (5)Typical VOHV (output VOH undershoot) >2V @ VCC = 3.3V, Tamb = 25℃ ; (6)Output capability: standard; (7)ICC category: flip-flops.