Product Summary

The EPF10K130EQI240-2 is an embedded programmable logic device. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, the EPF10K130EQI240-2 provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.

Parametrics

EPF10K130EQI240-2 absolute maximum ratings: (1)On the conditions of with respect to ground, VCCINT Supply voltage: min=–0.5 V, max=3.6 V; (2)On the conditions of with respect to ground, VCCIO: min=–0.5 V, max=4.6 V; (3)VI DC input voltage: min=–2.0V, max=5.75 V; (4)IOUT DC output current, per pin: min=–25 mA, max=25 mA; (5)On the conditions of no bias, TSTG Storage temperature: min=–65℃, max=150 ℃; (6)On the conditions of under bias, TAMB Ambient temperature: min=–65℃,max=135 ℃ ; (7)On the conditions of PQFP, TQFP, BGA, and FineLine BGA packages, under bias, TJ Junction temperature: max=135 ℃.

Features

EPF10K130EQI240-2 features: (1)Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device: Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions; Dual-port capability with up to 16-bit width per embedded array block (EAB); Logic array for general logic functions; (2)High density: 30,000 to 200,000 typical gates; Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity.

Diagrams

EPF10K130EQI240-2 block diagram

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